Re: AD9361+Zedboard and AD9361_iiostream example
Looks like the kernel mounts the FAT partition Read Only.It might be that the partition is corrupted.Can you plug the card into a Linux host and run fsck.vfat -y /dev/sdX1 -Michael
View ArticleRe: AD9361+Zedboard and AD9361_iiostream example
yes i can Michael // for sdb1[root@Host-001 dev]# fsck.vfat -y /dev/sdb1dosfsck 3.0.9, 31 Jan 2010, FAT32, LFNThere are differences between boot sector and its backup.Differences:...
View ArticleRe: ADSP-21261SKBCZ150 debug/program
Hi Vinod, I have a few additional suggestions. If you do not already have a board designed, I would consider looking at one of the newer SHARCs, one of the ADSP-2147x DSPs might be a better choice....
View ArticleRe: ADV8005 DDR2 Loopback issue
Hi Hank, This is the exact same question that as asked and answered last week: https://ez.analog.com/message/160905#160905 Dave
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Re: ad-fmcomms1-ebz programming FPGA
Thank u so much sir for ur guidance..I will follow the steps told by you and will reply you if there are some issues..
View ArticleAD7960 : data set up / hold times in ref design
In the docs for the AD7960 , is a set of Verilog / Xilinx reference files for how to interface to the AD7960. Great, Looking at the echoed clock version, as it seems the easiest, I can not see any...
View ArticleRe: ADV7393 settings question
Hi Lou, ADV7393 is strictly a digital to analog converter. It can't change the input format in any way so It's not possible to do what you are asking with ADV7393. There isn't any standard for how to...
View ArticleRe: Simulink ZC702 AD9364 fmcomms4-ebz
Hi, ACozma, Thanks for your reply. I used the AD9361 Simulink block and config file, but I got the following error. MATLAB System block 'ad9361_sim/MATLAB System' error occurred when invoking...
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AD8554 - Gain Bandwidth Product doesn't depend on Gain
Hey folks, I designed the following amplification circuit: The amplification of this circuit is set by R6. The higher R6 the higher the amplification. BUT the higher the amplification the HIGHER the...
View ArticleRe: AD7960 : data set up / hold times in ref design
I should add. There is a UCF file, BUT : it only contains the pin definitions and one clock timing constraint NET "CLK" TNM_NET = sys_clk_pin;TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;...
View ArticleRe: Linux OS Booting Fail
Hi, Dragos, I follow Linux with HDMI video output on the ZED and ZC702, ZC706 boards [Analog Devices Wiki] command to create my file. I used "make zynq-zc702-adv7511-xcomm.dtb" for my file.Regards tasi
View ArticleRe: Vdd2(Secondary side) question for ADuM1300 CN0064
Kaos, The ADuM1300 supply current depends on the supply voltage on both sides of the part as well as data throughput. What maximum baud rate must be supported, and what are the supply voltages? DaveC
View ArticleRe: AD9361 ADC Clock Configuration using No-OS
Hi Dragos,Let's assume I am using a Square root raised cosine at 200kHz cut off and I have gone over the matlab filter design wizard. since am using No_OS Sw the next steps are1. to make change (0-1)...
View ArticleRe: Simulink ZC702 AD9364 fmcomms4-ebz
Hi David, The error is related to loading the .dll library that handles the communication with the device. Can you please make sure that the library is properly installed by following the steps from...
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Re: AD8554 - Gain Bandwidth Product doesn't depend on Gain
Andre, Consider it as a summing amp and calculate the noise gain with R6 at min and max. BTW, The AD8554 is a first generation AZ part. I would use the AD8630. Harry
View ArticleAD9368
I'm trying to figure out how to go about calculating the input power / dynamic range of the AD9368 front end. I need to put an LNA on the front end between the antenna and the AD9368 and want to...
View ArticleADT7310 output variation
What would be the expected peak to peak output temperature variation of the ADT7310 if the temperature it is measuring is held constant ? I see there is a "repeatability" specification listed for the...
View ArticleRe: SYSREF duration for AD9625
Hi Derek- Yes, you are correct in your analysis. Only the rising edge of SYSREF is used as the latched event to the sample clock. (This is the default setting, as the falling edge could also be...
View ArticleRe: Does the AD9625-2.0EBZ work with the Xilinx evaluation board VC707?
Hi Gonzalo- Principally, the JESD204B interface is the same for both AD9625-2.5EBZ and AD-FMCADC2-EBZ FMC. The form factor, power supply and the front-end configurations are what separate the two...
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