Hi Derek-
Yes, you are correct in your analysis. Only the rising edge of SYSREF is used as the latched event to the sample clock. (This is the default setting, as the falling edge could also be alternately selected in the SPI map)
Practically, the pulse for SYSREF only needs to minimally meet the SU/HLD time relative to the sample clock. In most cases though, the pulse width would be much longer in duration. For the typical case, it would span many sample clock cycles and therefore the hold time would not be particularly relevant (only the setup time would be relevant).
Let me know if you have any more questions about this.
Thanks,
Ian Beavers