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Re: EVAL-ADAU1701MINIZ: SigmaStudio's EQs control wrong frequencies
Hello Prius, What is the sample rate set to within the SigmaStudio schematic? This is important in order to generate the proper download parameters for the filters. What are your settings for the...
View ArticleRe: AD9361 RX_FRAME and TX_FRAME signals in FDD
Yes, the mode is controlled by FDD External Control Enable bit in register 0x015. You can read more about this mode (FDD Independent Control) in UG-570 pg 28.
View ArticleRe: Building fmcomms2 in Vivado 2014.2
Yes, I did update the core versions in the tcl before building in 2014.2. Ok I have to go with 2013.4. Thanks
View ArticleHow to I implement non-blocking calls for receiving UDP on Blackfin?
Hi, I'm currently working on an application which receives and mixes multiple RTP streams on different multicast addresses. I have several threads running alongside one another and they all...
View ArticleRe: Re: AD9520-1 Eval Board - layout files available?
Hi George,Attached are images of the 4 layers in .pdf form. Let me know if any details that you need are not showing here. The coloring slightly distorted when I saved them as .pdf's.Regards,Kyle
View ArticleRe: dxe works ok but ldr doesn't run
I found the problem; The issue was to do with the fact that i was not properly initialising my SDRAM or properly organising my heap usage. When creating a simple LED Blink application my memory usage...
View ArticleRe: AD9525 reference clock configuration
Hi, REFA: Yes, you want to remove the 50 ohm resistor and leave C111 present.REFB: Yes, you want to remove the ac coupling capacitor and the 50 ohm termination.Regards,Kyle
View ArticleRe: AD9139, DAC latency from input to output
I will look into this and get back to you.
View ArticleRe: AD9102 minimum output frequency?
At the max sampling frequency of 180 MSPS, the part can do about 10 Hz accuracy with 24 bits of tuning word. I don't think it will do it.
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Hittite PLL components in ADIsimPLL
I'm using ADIsimPLL version 3.60.10, and noticing that there doesn't appear to be any support for Hittite PLL or phase detector components. Are there any plans to include support for Hittite PLL...
View ArticleRe: AD9361 VDD_INTERFACE
HI tlili, Yes it is there, Since i am using LVDS (2.5V) interface. I am connecting my data lines, control lines 7 SPI to 2.5V bank of FPGA. Is that ok? or am i wrong ?Please give some clarification on...
View ArticleRe: Using a iCoupler gate driver as a solid-state relay
Hello Mark,I really like the idea:It would be VERY interesting if ADI would consider making a packaged SSR using their isoPwr and iCoupler technology. This would provide a nice building block for use...
View ArticleRx Sample Streaming on Zc702 and FMC2
Hello, I was wondering if there is an example project/step that allows user to stream complex baseband samples from ad9361 to DDR memory connected to zynq chip on Zc702 eval platform mated with FMC2...
View ArticleRe: Need help with the power supply for AD7634
Mikhail,I just stumbled onto your ADIsimPower Excel issue comment.We may have fixed the issue already but in some instances the language setting of your operating system (not Excel) affects how Excel...
View ArticleRe: AD9822 noise
In addition to Harry's comments, you should also try adjusting the phase of the ADCCLK signal to see if the noise is reduced. The CDSCLK/ADCLK waveform quality is also important- you don't want to see...
View ArticleAD9910 basic configuration
Hi all, I want to help with a basic configuration of AD9910. I inherited a board with this chip after colleague who left our company.The last three days I try to configure the AD9910 into a single tone...
View ArticleRe: ADV7180 2xOversampling and LLC
Thank you for your kindly reply.I understood how to change frequency from external 28.636MHz to 27.0MHz of LLC by internal PLL. ADV7180 change s-video signal from Analog to Digtal by ADC, in...
View ArticleRe: Is AD8302 a lock-in amplifier?
I have just realised that the output bandwidth is 30MHz and my modulation frequency is 3MHz. So I have put in an external capacitor 100pF on PFLT (C8) to lower the output bandwidth to 0.3MHz. This has...
View ArticleRe: Sample Rate on the AD9361
I realize it is not in the data sheet that is the reason for my post.We have the manuals UG-570 and UG-671, but it is still not clear to me what the limits for the clock dividers and filters are.What...
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Re: Sample Rate on the AD9361
in UG 570 Table 10 pints out some common clock rates but does not give any limits. For example for LTE 20 it has a sample rate of 30.72 and the BBPLL is 983. but it does not cover what is the sample of...
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