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Problem about the connection of BF609 and ADC

Hi:    I meet a problem when I  try to use BF 609 to read ADC data from EPPI. The EPPI CLK is 40MHz, and the SCLK of BF609 is set as 50MHz.The DMA is work well, but there is no data be read into the...

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Re: zedboard fcomms1-ebz interfacing

helloI am following the discussion..I am working on zedboard with ad-fmcomms1-ebz..My need is to transmit digital data from zedboard through fmc to ad-fmcomms1-ebz and receive the transmitted digital...

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Re: Changing the Reference Design for the AD-FMCOMMS1-EBZ

hello..I am following the discussion..I too had a same doubt of transmitting signals to DAC of ad-fmcomms1-ebz..Can u help me on how to create a core that generates 8 samples at a time (4 for I and 4...

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Re: AD8554 - Gain Bandwidth Product doesn't depend on Gain

Hey, thanks a lot for your time! I was stuck with this for quite a while. Problem was, that the noise gain is rarely mentioned anywhere if you do not look for it in particular. So again, thanks a lot...

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How to calculate the coefficient of "bass boost" module in ADAU1701?

Hi everyone,     I'm using ADAU1701 and would like to control it with the MCU as the host.As I am going to use "bass boost" in my schematic,but I  can not figure out the formula to calculate all the...

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ADV212 EIRQFLG doesn't reset

Hello! I'm trying to use ADV21, I make all according to fig.12, page 17 of Programming guide. I have read correct firmware ID=0xff82. Then I try to reset IRQ flags by writing to direct address 0x6...

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Re: DVI to VGA active RAMDAC using ADV7123

how would i investigate the right part? like i said i dont really know much about designing hardware stuff, so i dont know much about FPGAs or how to program them, i only know software programming (C,...

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Re: accelerometer for induction motor vibration

Great information, Neil! The following article might be useful as well:http://www.analog.com/library/analogdialogue/archives/48-06/vibration_monitoring.html

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Re: ADIS16251 Screw Torque and Bias

In general, MEMS gyroscope's bias is sensitive to change in its package stress profile, which can happen through tightening the screws down on the PCB. So, this is not a large surprise. 

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Re: ADV7611 EDID configuration

Thank you for the support. This is strange since the original file was according to the script provided by Analog Devices.Is there any change in the DTD between the original file and the new one. We...

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Using no OS driver with custom h/w in verilog

Dear Support Engineer, I am having AD-FMCOMMS1-EBZ with ML 605 board. I have run No-OS driver successfully and able to run its API.I have my custom block of OFDM written in verilog. I want to interface...

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ADN4605 NRZ and PAM data support

  Dear SupporterFrom the ADN4605& ADN4604 DS, it looks that  it supports only NRZ data.  Will it support PAM data?ThanksFreddy 

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AD8177 AD8175 design support files

Dear supporterAre there design support files for the AD8177/5?If not, what is available to help my customers?Eval board documentation, Schematics? SW? Scripts etc.Nothing of the above is found in ADI's...

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Re: Auto detect input

Hi Chris, I have been crazy busy so only now had time to look at this to convert to a mono input. Im a little confused how to deal with the and gate and nand gate any help would be greatly appreciated...

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Re: Sigmastudio algorithms

Bump for Miguel as i really could do with this block

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Re: ADV7441a TMDS Equalization

Hi Alex, I know the recommended settings document has a flowchart that reflects the above settings. What document are you referring to? -Matt

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Re: ADL5511 Input Coupling

The 100 pF cap is looking into an ohmic impedance of between 200 and 300 ohms over your frequency range of interest (see Fig 9). So at 30 MHz that means that the 100pF cap is forming an input high pass...

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FMCDAQ2 and FMCADC2 availability

Hi,I tried the following Q in "FPGA Reference Designs" a few days ago but no response. Are they all at X-Fest?These FMC cards have the AD9680 and and AD9625 ADCs so maybe this is the better forum to...

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Re: ADV7441a TMDS Equalization

 ADV7441A SD/HDTV Video Decoder, Component and Graphics Digitizer with 2:1 Multiplexed HDMI Receiver Hardware Database Manual Rev J June 2010 

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Re: AD9361 ADC Clock Configuration using No-OS

Hi Adrian, Here is the main.c... the bitstream reflects the same raw HDL design as yours (all works OK with 30.72MHz sampling rate, even at 8.666667MHz sampling rate all fine as far as the JTAG clock...

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