Re: AD9361 ADC Clock Configuration using No-OS

Hi Adrian,

Here is the main.c... the bitstream reflects the same raw HDL design as yours (all works OK with 30.72MHz sampling rate, even at 8.666667MHz sampling rate all fine as far as the JTAG clock is lower).

meanwhile, can you share with me your .bit and probes files .lxt?

Thanks Adrian,

Ahmed,