The schematic is somekind of "standard" and the quality depends of the used components I could make a demo PCB right now with e.g. an inductive coupling to feed the area with a RF-signal (getting wild ideas now). The ADM7154 is indeed nice. But in order to use in combination with an AD9910/AD9912 I think a bit over the top for a 2-layer design. And quality depends also on the 1Ghz clock oscillator. The most hard part is selecting the right footprint for a component where I can mount other components on for experimenting. But as I now have, does the component selection looks ok?
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Re: ADP150 and capacitor choise
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Re: HMC833 power reduction with Doubler
Once locked on 3GHz with doubler off (-6.5 dBm output) check the frequency change to 3.5GHz follows the following sequence. I assume frac-n mode, 50MHz reference, R=1, autocal is on:
Set VCO to 1750 MHz
- Reg 03h=23h
- Reg 04h=0, after this write the HMC833 locks to 1750 MHz
Turn doubler on
- Reg 05h=18h, output frequency changes to 3.5GHz
- Reg 05h=0h, part loses lock
- Reg 04h=0, part locks to 3.5 Ghz. Output power should be around -4 dBm.
Steps 2 and 3 are only required if you want to change frequency again after turning the doubler on.
Keep in mind there is a very high 1/2 harmonic with doubler on. When locked at 3.5 GHz you will see a 1.75 GHz harmonic around -7 dBc.
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Updating AES-KCU-JESD-G in Vivado
Technical Goals require operating in latest Vivado and System Generator Versions. Need to update Analog Devices Ip to be compatible.
Updated to Vivado 2016.4 MatLab 2016b Design KCU105-- IP Status OK
Simulation results in errors
system_axi_ad9144_core_0 while processing axi_9144_core
for 20 axi files
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Re: Enabling AD9371 Rx through Linux Driver
I see, that makes sense. So it would be
[Rx1-I, Rx1-Q, Rx2-I, Rx2_Q]
as the first 8 bytes of the buffer? Meaning in a 4096 byte buffer, there would be 512 samples at a time?
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Re: overlay / virtual memory methods
Hi Miguel,
yes it's an application for effect processing for guitars or instruments in general.
Alex
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Re: Question on calculating Wh/LSB on ADE7953 active energy calibration
What does the signal input 500mV mean?
what does " a dynamic range of 3000:1 means?
how do I calculate the maximum current and base current for ADE7953?
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Re: I have an SDP-H1 connected to a eval-ad777 board; I want to connect to it using the visualanalog software but that software does not list this board in its drive list; can I download a driver for this board?
Yes, correct. It may be that I simply need to use the ACE software. I am just getting started with these boards and simply want to acquire discrete ADC samples (anywhere from 10 seconds to 4 hours) from 4 analog inputs and save them for MATLAB analysis. There is a lot that Analog Devices has to offer, so I am a bit lost understanding how best to interface to this development platform. Any help you can provide will be greatly appreciated.
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Re: AD1939 via Electret Mic Preamp Design
Excellent point about the phase shifting in the hardware - that would definitely introduce more complications! I'll utilize an FIR filter for each data stream. I'm thankful the T.I. preamplifier design is a viable choice! Thank you for the assistance Dave!
Jordan
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Re: ADP150 and capacitor choise
As seen in the pre-design, I have the C4 on the top-layer and FB on the bottem-layer what is the same layer for the supply circuits. But it is an overthinking worth at which point the FB/C4 filtering takes place. Design rules I have made are 1 separated supply for analog and 1 for digital (also ground), no crossings/long lines at regulated supply, exception is the RF lines with an 1206 0Ohm with the spacings filled as ground. The intention is to connect analog/digital ground together is under the DDS with FB's. Due this the internal ground of the DDS will also getting a lower internal resistence. BTW, the big square around the DDS is a heathsink for stabilizing frequency drift. The complete project will be 2 PCB's. 10x10 (DDS) and 10x6 (filter/amplifier). This is done to easily select/change the desired component for a specified frequency. And it will fit into an Eurocard format canning. The digital part will be controlled by a simple STM32F1 for bitbanging the selected protocol and doing the control lines. This STM will be serial controlled due a fiber by another controller at least there is 100% separation. You have now an idea on what I working at Jason. But it is freetime hobby so give me a year to finish it completely.
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Re: Trouble booting Linux on Mini-ITX with FMCOMMS4
I concur with Csomi. The latest commit appears to have worked here for me. The spdif and i2s resources are now mapped as expected. Here are the steps I took:
git clone https://github.com/analogdevicesinc/hdl.git
cd hdl
git checkout b59549053c9212adba1384dd8cf2245c622d7c52
gedit projects/scripts/adi_project.tcl
<changed xc7z045ffg900-2 to xc7z100ffg900-2>
cd library
make
<correct component.xml in spdif_axi_tx, spdif_axi_rx and axi_i2s_adi folders as done previously>
cd ..
make fmcomms2.mitx045
And here's what I got:
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Re: AD7621 problem with serial interface
Hi ir2017,
Make sure you set SER/PAR to high. Can you share some screen shot on the SDOUT,SCLK,and other digital interface?To give us more view of the problem.
Regards,
Lloben
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cf_axi_adc failing to probe on 0x80000000 failed with error -5
Trying to get the AD9361 working to Send and transmit but the cf_axi_adc driver is failing.
[ 3.339512] ad9361 spi32766.0: ad9361_probe : enter (ad9361)
[ 3.537103] ad9361 spi32766.0: ad9361_probe : AD936x Rev 2 successfully initialized
[ 3.995165] SAMPL CLK: 61440000 tuning: RX
[ 3.999182] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.003599] 0:# # # # # # # # # # # # # # # #
[ 4.008026] 1:# # # # # # # # # # # # # # # #
[ 4.012453]
[ 4.013939] ad9361 spi32766.0: ad9361_dig_tune: Tuning RX FAILED!
[ 4.418229] SAMPL CLK: 61440000 tuning: TX
[ 4.422245] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[ 4.426662] 0:# # # # # # # # # # # # # # # #
[ 4.431089] 1:# # # # # # # # # # # # # # # #
[ 4.435516]
[ 4.437000] ad9361 spi32766.0: ad9361_dig_tune: Tuning TX FAILED!
[ 4.443304] cf_axi_adc: probe of 80000000.axi_ad9361 failed with error -5
As far as I can tell the device tree matches the address in the hdf file? Any idea what area I can tackle to get this completely configured?
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Re: About the STDI_INTLCD of ADV7441A
Thank you for your respond! I have read that forum post yet. I think I met the similar problem. Now, I just use continuous STDI mode to get INTLCD, and one-shot mode to get ohter four params. That will reduce the error rate of INTLCD. But I still don't understand which causes the problem.
I have read HW handbook again. After I set Chip Reset according to ADV7441A EDID_Rev0.pdf, I set the ADC0/1/2/3 to select input pins, then I use the one-shot mode to get STDI params. will some other registers be set before use STDI one-shot mode?
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AD9361 RSSI weight computation
Just saw there is an update on RSSI weight computation
drivers/iio/adc/ad9361: Fix RSSI weight computation · analogdevicesinc/linux@a8201cf · GitHub
Can you explain little more about this fix? Do I need to update my linux driver?
Benson
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hmc1033,please help me, thanks
I configuration my hmc1033 board with the procedure,generation 500MHz clock:
HMC1033_Write(0x0A,0x2006); //reg A
HMC1033_Write(0x08,0xC1BEfF);//reg8
HMC1033_Write(0x0F,0x81); //reg f
HMC1033_Write(0x07,0x14d); // reg7
HMC1033_Write(0x0B,0xF8061);//reg b
HMC1033_Write(0x0C,0x0); //reg c
HMC1033_Write(0x02,0x02); //XTAL R,Step1 reg 2
HMC1033_Write(0x06,0x2003CA);//A/B Mode,Step2 reg6
HMC1033_Write(0x09,0x10F264);//Charge Pump,Step3 reg 9
HMC1033_Write(0x05,0xFf88); // vco 01
HMC1033_Write(0x05,0xF98); // vco 3
HMC1033_Write(0x05,0x48B8); // vco 7
HMC1033_Write(0x05,0x0); //vco 0
HMC1033_Write(0x03,0x50); //reg 3
HMC1033_Write(0x04,0x0); //reg 4
HMC1033_Write(0x05,0x210); //VCO Subsystem,Step4 vco2
in the first palce,my hmc1033 can generation 500MHz clock,but the lock Detect pin is still low ,and a few minutes,then output change,like the figure 2.. please help me why?and how to configuration the hmc1033?
thanks!!
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How to connect a 3.3V LVCMOS clock (single-ended) to ADCLK944 input?
I am use a 3.3V LVCMOS clock (single-ended) connect to ADCLK944 input.
The ADCLK944 datasheet said "The input can accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs".
That's mean we must dc-coupled the 3.3V LVCMOS clock input, but how to connect it to ADCLK944's CLK pin? and how to connect the unused the CLK- pin? and the VT pin?
Thanks!
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ADV7611 12BIT SDR ITU BT656 Mode 2
Dear my friends,I'm using amcap to capture adv7611 output video.It's fine to acquire video when adv7611 works in 16 bit SDR ITU-R bt656 4:2:2 mode 0,Since the video source inupt to adv7611 is 12bits black white video,and the 16 bit SDR ITU-R bt656 4:2:2 mode 0 has only 8 bits Y7-Y0. So the video acquired is 8 bits black white video not as clear as 12 bits black white input video.To solve this problem,I found that adv7611 has ability to work in 12 bits SDR ITU-R bt656 mode 2 which is 12bits Y11-Y0 output. So my question is how to modify amcap to acquire 12bits bt656 mode 2 video?I did not found any appropriate macro define MEDIASUBTYPE in uuids.h for this.Any help will be greatly appreciated.
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Re: Video is distorted after some days in Encoder ADV7340
Hi,
Do you have any update on the follow up questions?
Can you able to resolve the problem?
Best Regards,
Jeyasudha.M
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Re: Regarding AD9361
Hello Anki,
To my knowledge, we don't enable the HDL IQ correction block in the fmcomms2/3/4 reference design.
The HDL provides support for it and it can be controlled through the ADC Channel registers (REG_CHAN_CNTRL , REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2). You can also use IQ correction internal to ad9361.
You can find more information regarding the IQ correction at:
I/Q Correction [Analog Devices Wiki]
For FMCOMMS5, IQ correction is used for IQ rotation : I/Q Rotation [Analog Devices Wiki]
Regards,
Adrian
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Re: Low maximum Tx output power
In attachment is schematic of Tx output structure. On scheme balun is 5400BL15B050, but in real it is 1850BL15B050S.
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