A note to anyone referencing this thread in the future: via private support ticket, I learned that the BF537 HRM has a typo. `_BOOTROM_Boot_DXE_Flash` should be all caps `_BOOTROM_BOOT_DXE_FLASH`. This is defined in defbf537.h and does not require a manual definition.
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Re: How to load new program from c for BF537
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ADPD105 TIA ADC mode configuration
Greetings.
I have an EVAL-ADPD105Z-GEN kit with me.
I have tested and obtained a fairly noise-free PPG from the EVAL board. However, I would like to use the TIA ADC MODE of the ADPD105 with the input to the trans-impedance amplifier as a sine wave.
The connections that I made are:
--> Function generator positive to PD1-2 pin with a 100 kilo ohm resistor in series to prevent the TIA from saturating
--> Function generator negative to PDC
--> I am giving a 1V peak-to-peak sine wave as the function generator output.
--> To bypass the band-pass filter, I am using the ADPD OpenMarket Wavetool to write the values 0xAE65 to the register 0x43 and 0x45 (register values have been taken according to the datasheet's specifications).
--> I am also writing 0x1CB6 to the registers 0x42 and 0x44 in order to configure the integrator as an inverting buffer (again according to the datasheet's specifications).
After performing the above steps, I find that the I am getting no output on the Graph View of the ADPD OpenMarket Wavetool.
Any help with this would be greatly appreciated.
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Re: Overlay manager example to overlay VISA code
Hi Jithul,
I am looking for a overlay manager for ADSP-21489.
Also I don't see the above example has overlay for VISA sections i.e. seg_swco
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Re: Running multiple applications on BF537
A note to anyone referencing this thread in the future: via private support ticket, I learned that the BF537 HRM has a typo. `_BOOTROM_Boot_DXE_Flash` should be all caps `_BOOTROM_BOOT_DXE_FLASH`. This is defined in defbf537.h and does not require a manual definition.
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Re: Format of IIO scope FFT I/Q data and converting to dBFS
Hi,
You are right it is 12-bit signed integer. So your full-scale value is 2048. dBFS is a measure of a specific signal power relative to the full-scale signal power. How exactly to calculate the dBFS depends on what on want to know the dBFS. E.g. over the full signal or only certain frequencies contained in the signal. You should be able to find plenty of online resources that cover your specific case.
- Lars
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Difference in pn monitor in ml605 design and vc707 design of ad9361
Hello,
We are curious to know why is there a difference between the pn monitor code in the ml605 design (fpga-hdl-xilinx-master) and the vc707 design(github analog device hdl) ? We found that a bit reversal function is used in the ml605 design. Why was it removed in the vc707 design? Was it because of the change in device primitives of iodelay of Virtex6 and Virtex7?
the files we compared were
(github/hdl/library/common/ad_pnmon.v) and
(fpga_xilinx_master/cf_lib/edk/pcores/axi_ad9361_v1_00_a/hdl/verilog/axi_ad9361_rx_pnmon.v)
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Re: OP295 SUPPLY CURRENT Distribution
What can you do with a histogram of supply current?
The part is 100% tested for supply current, and every part you get will be less than 150 uA,
so if this is a battery powered application, you have to design for some parts to be 149 uA.
If this is a new design, I would not choose a 25 year old part, but rather the ADA4096-2,
which is six years old, less money, faster, and a guaranteed 100 uA over temperature.
Harry
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Re: overlay / virtual memory methods
Hi Alex:
You are correct, the Sharc and more low level coding are the better tools for your purpose (generic plug/play dynamic environments). The Sigma could do it but it wouldn't be pretty.
what's your application? Musical Instruments?
Thank you
Miguel
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Re: About the meaning of In-run Stability and Bias Repeatability.
Which products are you considering for your application? In general, we use IEEE's definition for In-run Bias Stability (IEEE-STD-972-1997). This parameter represents the best accuracy available when estimating the gyroscopes bias under stable inertial and environmental conditions. Bias Repeatability represents an estimate for long-term aging. The product data sheets which use this parameter, offer extensive information in the footnotes, as to the testing that was performed in order to make this projection.
Hope that helps!
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Re: About the meaning of In-run Stability and Bias Repeatability.
With respect to you asking how you can "calculate bias repeatability," that really isn't a parameter you can calculate. Perhaps this was missed in my previous comments, but this represents a long-term aging estimate. In every data sheet that I have personally written, I have included very detailed footnotes that explain the testing that goes into the bias repeatability number. If you have any questions on one of those footnotes, please let me know, but please provide a clear reference to which product and data sheet you were referring to.
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Re: About the meaning of In-run Stability and Bias Repeatability.
Great job in finding the FAQ. That shows you how you can measure and calculate in run bias stability. Can you check that out and let me know if you still have any questions on that particular parameter?
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Re: No OS example code and common.c file for zc706
Try below sequence for clock initialization in 'headless.c'.
/**********************************************************/
/************ Clock Initialization Sequence *************/
/**********************************************************/
puts("AD9528 initialization");
AD9528_initDeviceDataStruct(&ad9528Clock,122880000, 30720000, 122880000);
AD9528_resetDevice(&ad9528Clock);
AD9528_initialize(&ad9528Clock);
ad9528Locked = AD9528_waitForPllLock(&ad9528Clock);
if(ad9528Locked == 0)
{
puts("clock locked");
}
else
{
puts("clock not locked");
}
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Re: ADP150 and capacitor choise
The sch looks good! If your application needs high performance of noise level, ADI also has ADM7154, which RMS noise is only 1.6uVrms compared to 9uVrms of ADP151. Thank you.
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Re: ADIS16480 UPDATE RATE FOR EULER ANGLE
ADIS16480 Datasheet (rev E), page 26 (PDF), talks about the update rates for magnetometers, which do influence the angle measurements.
http://www.analog.com/media/en/technical-documentation/data-sheets/ADIS16480.pdf#Page=26
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ADV7630 Hotplug Detect Issue
Hello
Can anyone help with this problem regarding the ADV7630?
I am using demo pcb for the ADV7630
I connected 2 sources and 2 monitors:
Source 1 to HDMI Port A
Source 2 to HDMI Port B
Monitor 1 to HDMI Port Tx A
Monitor 2 to HDMI Port Tx B
If I disconnect source B on HDMI Port B, Source A will blink before restoring video on Monitor 1, and vice versa. How can I prevent this blink from occuring when disconnecting a video source?
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Re: BF561 Input/Output Clock Skew
Yes, but only if it's a constant skew. If there is some element of randomness, i.e. it could be different every time we power on or reset the clock, then all bets are off.
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Re: ADV7343 RGB and CVBS?
I tested various RSETs in the lab and when running RGB video I do need to use the full drive setting with RSET of 510 ohms to get a full 700mV video output swing. There is a bias but as discussed before this is fine since the monitors are AC coupled. The key for me was getting the proper 700mV swing.
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Re: HMC833 power reduction with Doubler
I am using a custom board designed on the lines of the evaluation board. I've connected the RF Out to Pin 28.
The doubler setting was accessed through the VCO_Reg 03h register.
a) Bit0 - 0 & Bit[4:3] - 00 is the setting for Activating Doubler (for f > 3GHz)
b) Bit0 - 1 & Bit[4:3] - 10 is the setting for Deactivating Doubler (for f < 3GHz)
I tried generating 3GHz in config b, and I got -6.5dBm. This is almost matching with the evaluation board result you got.
However when I load config a, power drops to -21.5dBm.
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Re: ADV7343 Test Pattern Issue
Dear Anthony,
Hi, thanks for your reply. To elaborate the timing parameters, here is the generic LCD configuration entry in the host machine:
| { | |
| /* 800x480 @ 57 Hz , pixel clk @ 27MHz*/ | |
| "MY-LCD", .ref_rate=57, .hactive=800, .vactive=600, .pixel_clk=37037, | |
| .hback-porch= 40, .hfront-porch = 60, | |
| .vback-porch = 10, .vfront-porch = 10, | |
| .hsync_len = 20, .vsync_len = 10, | |
| .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | |
| .vmode = FB_VMODE_NONINTERLACED, | |
| .flag = 0,}, | |
{ |
My intention is to get the 4bit RGB LCD display signals interfaced to this encoder and converting it to CVBS. Host machine generates a 24bit RGB signals according to the timing parameters we assign in LCD entry.
1. So according to what you say, the timing should be compliant with NTSC standard, not the lcd parameters ? I am using a 800x480 generic lcd panel from SEETECH.
2. According to the datasheet, the sync signals should be in 'active low' mode, in otherwords the inverted version of the signals in the oscilloscope view right ?
3. Where can I find these full timing parameter list for NTSC 525i ?
Thanks in Advance
Anuradha
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Re: ADE7953 - reading AWATT
Hi,
The AWATT register is a signed register.So the variable used to store the power value should be signed. Look at the MSB to determine if its a negative/positive numer.
In the last case, When Angle =-179, AWATT= 0x B51CFC which is negative because the MSB is 1. The decimal equivalent comes out to be -4907780.
A good way is to read the 32 bit register into a signed variable and let the compiler handle the conversions.
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