Hi Johannes,
The divide down value is based on the internal core clock freqency of 49.152 MHz, not the 12.288 MHz MCLK input. A divide by 16 should generate 3 MHz clock (49.152 MHz/16 = 3.072 MHz).
Based on the ability to use OUTPUT_BCLK as a master clock, and the datasheet recommendation for connecting the input/output LRCKs and BCLKs together, I would think the CS4272 serial ports can be configured as a I2S slave if you want to use the "MP11=BCLKOUT" master clock option in the system.
-JT