Hello Anki,
To my knowledge, we don't enable the HDL IQ correction block in the fmcomms2/3/4 reference design.
The HDL provides support for it and it can be controlled through the ADC Channel registers (REG_CHAN_CNTRL , REG_CHAN_CNTRL_1, REG_CHAN_CNTRL_2). You can also use IQ correction internal to ad9361.
You can find more information regarding the IQ correction at:
I/Q Correction [Analog Devices Wiki]
For FMCOMMS5, IQ correction is used for IQ rotation : I/Q Rotation [Analog Devices Wiki]
Regards,
Adrian