Leonard:
Have a look at:
That points to here:
http://wiki.analog.com/resources/fpga/docs/hdl/regmap
The reason register accesses (HDL/Device) are intertwined, is that is what is required to make it work properly.
There are options to make things a little cleaner.
http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation
Depending on what your platform needs.
- Robin