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Re: About AD9548 DPLL register setting

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@Hi Paul,

 

Thanks for your reply. I have try you suggested on EVB , it's works on DPLL free run once setting 255.76 MHz.

Then divide 16 on Q0 ,Fout =14.11 MHz.

But, how can I used it on profiles 0 which setting as below ? Thanks.

   

ValueUnitMinimumMaximum
System Clock Period / Frequency972MHz5001000
Selection Priority007
Promoted Priority000
Nominal Reference Period / Frequency19.44MHz0.000001800
Inner Tolerance100ppm1100000
Outer Tolerance1000ppm100100000
Validation Timer10ms065535
Redetection Timer100ms065535
Feed Forward Divide (R)19219440000
Feed Back Divide (S)22062380
Feed Back Fraction (U)65099
Feed Back Fraction (V)10001023
(calculated - PFD frequency)1.023MHz
(calculated - DDS frequency)225.760MHz
Loop Bandwidth0.001Hz0.00151157.8947
Phase Margin30deg3088
3rd Pole Attenuation Offset0.000005kHz0.0000051023.15789
3rd Pole Attenuation3dB33
(calculated - alpha)2.96652E-12(-5.6 ppm)
(calculated - beta)-2.77179E-10(4.3 ppm)
(calculated - gamma)-3.58281E-10(2.3 ppm)
(calculated - delta)1.03671E-09(-17.0 ppm)
Phase Lock Threshold1000ps165535
Phase Lock Fill Rate321255
Phase Lock Drain Rate681255
(calculated - allowable jitter - RMS)1.006ns
(calculated - probability below threshold)0.68
Frequency Lock Threshold500ps15144.03292
Frequency Lock Fill Rate321255
Frequency Lock Drain Rate681255
(calculated - allowable jitter - RMS)502.787ps
(calculated - probability below threshold)0.68

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