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Re: Modifying HDL Design, FMCOMMS5 and ZC706

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Hi,

 

For the throughput the limit is pretty much the AXI HP interconnects on the ZYNQ. The AXI-DMAC itself is capable of transferring one word per clock cycle continuously as long as the destination is capable of accepting the data. It is possible to increase the throughput if necessary by splitting the transfers over multiple HP ports.

 

Yes, the IIO framework will make sure that the queue is kept filled up.

 

The length of a transfer is programmed into the DMA controller and currently there is no support for completing a transfer before all data has been received. TLAST is ignored by the the AXI-stream backend of the DMAC.

 

It is possible to abort a transfer from software, but this mainly meant for exception handling in case the source stops sending data.

 

- Lars


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