Now,I am tring to use adv212 in Raw Video mode & JDATA mode controlled by FPGA
After loading the firmware I check the SWAFLAG.It is FF82.Then I write 0xFFFF to EIRQFLG.VRDY becomes active after 2-5 ms. The problem is VRDY becomes inactive and never go active high after I send one frame pixel data to adv212.And there is no VALID assertion.
Below are given the registers I set.
// VCLK=MCLK=27Mhz
//I reference the programming guide Figure 34
PLL_HI<-0x0008
PLL_LO<-0x0004
WAIT_20ms
BOOT<-0x008A
BUSMODE<-0x0005
MMODE<-0x0005
//load firmware
STAGE<-0x0005
IADDR<-0x0000
IDATA<-firmware
BOOT<-0x008D
BUSMODE<-0x0035
MMODE<-0x0005
//set encode parameters
STAGE<-0x0005
IADDR<-0x7F00
IDATA<-0x0004
IDATA<-0x0503
IDATA<-0x0100
IDATA<-0x0000
IDATA<-0x0200
IDATA<-0x0600
IDATA<-0x000F
IDATA<-0x0001
//set indirect registers
MMODE<-0x0009
STAGE<-0xFFFF
IADDR<-0x0400
IDATA<-0x0004
STAGE<-0xFFFF
IADDR<-0x040C
IDATA<-0x0280 //640
IDATA<-0x01E0 //480
IDATA<-0x0000
IDATA<-0x0000
IDATA<-0x0001
IDATA<-0x0000
IDATA<-0x01E0
IDATA<-0x0000
IDATA<-0x0001
IDATA<-0x0280
STAGE<-0xFFFF
IADDR<-0x0448
IDATA<-0x003F
IDATA<-0x0022
BUSMODE<-0x0021 //I don’t know why BCFG<-b010 means RAW Video Mode
//why not BCFG<-b011 meas Simultaneous JDATA and Raw
//Video modes.The programming guide set 0x0021.
STAGE<-0xFFFF
IADDR<-0x1408
IDATA<-0x061A //EMOD0 the Programming guide set 0x0061
EIRQIE<=0x0400
Check FIRQFLG[10]=1
STAGE<-0xFFFF
IADDR<-0x1408
IDATA<-0x061B //EMOD0 the Programming guide set 0x0061
Check SWAFLAG <-0xFF82
EIRFLAG<-0xFFFF
//then wait VRDY assertion to send pixel data and wait VALID assertion to receive compressed data
There are some questions to ask:
1.I want to know how to use SCOM[3:0].Is there some documents?
2.I think there may be something wrong with my regs setting or timmings to send the pixel data to ADV212.But I don’t know where can be the problem.I also read the document about the dead zone in raw mode.
3.I set MMODE to 0x0005 for encode paramters setting and 0x0009 for indirect regs setting.Is that right?
4.DMA data width in BUSMODE reg must be set to 8bit or 16bit ?
Regards,
Liao