Thanks Dragos,
I used your SDK workspace, the bitstream and the .lxt and I am NOT having ILA issue. this is inline with what Xilinx proposed 'building the project from scratch'!!!. I will have to get back to the new HDL and SW sources and build the project from scratch. can you point me on the updated HDL and SW (NO_OS) repositories and instructions on how to build the HDL (vivado flow) including the libraries?
meanwhile can you rebuild a bistream with ILA depth of more than 65K please (plus the associated .lxt)? (I wasted too much time and I need to get GMSK signal samples for analysis)
Thanks and best regards,
Ahmed,