The factory code pin settings bypasses the REF CLK divide by 2 feature. This enables multiple devices to be synchronized, if desired.The reason, in normal mode, a master reset enables the REF CLK divider by default. Unfortunately, in normal mode this REF CLK divider is not reset via the master reset. Therefore, the SYNC_CLK between devices can be 180 degrees out of phase. For multiple parts to be synchronized, the SYNC_CLK must be phase aligned.
As far as the SYNC CLK output swing. The SYNC_CLK is a 3.3V CMOS output but the output driver is not meant to drive a low impedance trace with excessive capacitance. The SYNC_CLK might need buffering in that case.
