Hi MSCantrell,
Thank you very much for your reply and concerning.
At first for your question, target performance is 5~6 Mbps in current design, however it may increase to around 20 Mbps in near future of our scope.
Next, sorry to bother you again, there are several additional questions.
a) If using newer CMOS isolators, do we need or better to add any level adjusting between I2S and both side of CMOS isolators ?
b) For example ADuM7510 datasheet specify Maximum Data Rate under CL=15 pF, however when CL is bigger, assuming Maximum Data Rate has to be decreased but how do I estimate or calculate it ?
c) What if it needs level adjusting in above a), does it affects to Data Rate which can be achieved ?
Again, your helps and support would be very much appreciated.
Best Regards,