Re: ADV7343 - Input Clock Frequency

Guenter,

What about the control of ADV7611 output frequency by DR_STR_CLK[1:0], IO, Address 0x14[3:2] => 01 (Medium low (2×) for LLC up to 60 MHz).

Or else Suggest the video encoder which supports max. UXGA60 pixel clock.

Thanks,

Siva