Hi, Jebas.
It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbps allowing it to read an ADC result in less than 1 μs. You should not be worried about coupling digital noise into the converter as long as you keep the digital lines away from analog circuitry. It is always good practice to have a series termination resistor that can be adjusted to prevent overshoot on the digital lines. The optimum value of the resistor can be determined by experimentation or simulation if you have that capability.
Regards,
Karen