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Re: ADAU1701 noisy sine waves
Hi Jon, I also believe that the reconstruction filter is necessary. The top scope trace is after the eval board's filter (at its output mini jack), the second one below is directly from the...
View ArticleAD9915 output attenuation when driving FPGA. Explanation and solutions?
Customer Question: We are using a AD9915/PCBZ in combination with a Xilinx ZC702 eval board. We are using a Xilinx FMC XM105 debug board to access the clock and I/O pins on the FPGA. The sync clock...
View ArticleRe: AD5421 Offset Register
Hi BobR, How are you writing to the part? By that I mean the sequence of the commands that you are sending to the part. Would you be able to do the following in sequence?Do a software resetSet the...
View ArticleRe: edit hardwareconfiguration in graphical sigma studio?
Hello hubijo, Now I understand what you wish to do -- change the Master/Slave bit under control of the running DSP program (graphical signal flow). This would allow a self-booting ADAU1701...
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Re: Explanation of different parameters on EVAL AD5933EBZ Software and its...
Hi,You can start with what's in the eval software.A detailed explanation of the different parameters in the AD5933EBZ software can be accessed by pressing the “Help:How to use software” button. The...
View ArticleRe: ADI Sigmastudio question
Thank you for your question. Someone from DaveThib's team will respond to your inquiry shortly. Regards, Lisa
View ArticleRe: SigmaStudio Automatic Speaker EQ Usage
Thank you for your question. Someone from DaveThib's team will respond to your inquiry shortly. Regards, Lisa
View ArticleRe: ADAU1761 with ground-centered headphone configuration
Thank you for your question. Someone from DaveThib's team will respond to your inquiry shortly. Regards, Lisa
View ArticleRe: Automatic Room Correction/Tuning using SigmaDSP or ADAU1452?
Thank you for your question. Someone from DaveThib's team will respond to your inquiry shortly. Regards, Lisa
View ArticleRe: ADAU1961 pseudo differential input
Thank you for your question. Someone from DaveThib's team will respond to your inquiry shortly. Regards, Lisa
View ArticleRe: SSM3302
Thank you for your question. Someone from DaveThib's team will respond to your inquiry shortly. Regards, Lisa
View ArticleRe: The settling time of switching from CDS mode to SHA mode.
Hello , I'm sorry, I had a mistake."AD9982" is wrong and the question is about "AD9822". Could you tell me advice ? Thank you,ysuuzki
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Re: AD9915 output attenuation when driving FPGA. Explanation and solutions?
HI Lionel, Have you tried connecting at J9 without probing it. We're suspecting that it has something to do with your setup or the quality of cables that you are using. Checking at the last picture,...
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Modifying debug_nets.ltx file
Can i change the code inside debug_nets.ltx so that make the Vivado H/W manager load the Probe datas and bind them into virtual bus automatically?and if yes, how?
View ArticleHow could we have the detailed information about IIOSTREAM.C?
Dear all, I have found that iiostream.c can be an aid if I want to get the A/D converted data stream for a period of time. I would like to know whether the above judgement I make is agreeable. Besides...
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Re: ADV7611 custom resolution (2560x720)
Well, according to VESA CVT generator, it should be around 117MHz?ar
View ArticleRe: libiio ad9361-iiostream example
Hi Lop.ng, I am going to study the iiostream.c and try to modify it however I have no experience of C or C# programming in the environment of Ubuntu or Linux. Could you give me some advice? Regards,...
View ArticleMonitor and restart BF561
Hi, we got a problem when using BF561 for H.264 compression. We need BF561 to work continuously and if it failed we want to restart it automatically. So we use FPGA to monitor the working status of BF...
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