Thank you for your reply.
I saw that thread, but was hoping it didn't apply to me due to the thread title and my slowly developing confidence levels with XPS / Vivado. I gradually comprehend new information each time I re-read through these threads.
For added clarification -
While the FMCOMMS1 is spec'ed for a 200MHz TX bandwidth, the recently updated hdl must be modified for a larger bus width and rebuilt to achieve this bandwidth (ie. Fs = 491.52MHz, Interpolation = 1x)? What implications would this have for the using the Linux or no-OS drivers with Zynq? Do they need to be modified?
If I understand correctly, the Zynq DMA controller is only 64-bit maximum. In order to use the 128-bit bus, I would need to add an additional DMA controller via XPS, allowing the PL fabric to read the samples written to DDR memory by the Processing System (PS) section previously?
I think I can achieve my desired transmission signal with a single base-band IQ channel, but am not sure I understand why 2-channels would be necessary. Feel free to offer insight on this. Would a single DAC channel this alleviate the need to add a DMA interface to the PL fabric? Logistically, what modifications to the HDL and drivers would be necessary to implement a single DAC channel? Would this retain a 64-bit bus rather than needing 128-bit for the higher bandwidth?
Thanks again for your help and insight. Hopefully I am deciphering the thread details correctly as I combine the scattered details.