Yes, it's the standard reference design still in 2's complement mode.
The output of the software is the same except for the DAC test, which is expected.
Testing the DAC communication...
dac_setup: dac_clock(122.882MHz)
dac_sed: s0(0x0000AAAA), s1(0x00000000)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
dac_sed: s0(0x00005555), s1(0x00000000)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
dac_sed: s0(0xAAAA0000), s1(0x00000000)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
dac_sed: s0(0x55550000), s1(0x00000000)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
dac_sed: s0(0x00000000), s1(0x0000AAAA)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
ERROR: Addr(0x72) Data(0xAA)!
ERROR: Addr(0x73) Data(0xAA)!
dac_sed: s0(0x00000000), s1(0x00005555)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
ERROR: Addr(0x72) Data(0x55)!
ERROR: Addr(0x73) Data(0x55)!
dac_sed: s0(0x00000000), s1(0xAAAA0000)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
ERROR: Addr(0x72) Data(0xAA)!
ERROR: Addr(0x73) Data(0xAA)!
dac_sed: s0(0x00000000), s1(0x55550000)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
ERROR: Addr(0x72) Data(0x55)!
ERROR: Addr(0x73) Data(0x55)!
dac_sed: s0(0x00000000), s1(0x00000000)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xFF)!
ERROR: Addr(0x71) Data(0xFF)!
dac_sed: s0(0xAAAAAAAA), s1(0x55555555)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0x55)!
ERROR: Addr(0x71) Data(0x55)!
ERROR: Addr(0x72) Data(0x55)!
ERROR: Addr(0x73) Data(0x55)!
dac_sed: s0(0x55555555), s1(0xAAAAAAAA)
ERROR: Addr(0x67) Data(0xA0)!
ERROR: Addr(0x07) Data(0x04)!
ERROR: Addr(0x70) Data(0xAA)!
ERROR: Addr(0x71) Data(0xAA)!
ERROR: Addr(0x72) Data(0xAA)!
ERROR: Addr(0x73) Data(0xAA)!
DAC test complete.
The ChipScope output is a slightly-varying negative value which looks like the output below.
This is a step in the right direction, although I would have expected the output to look different. In an alternate test, I changed the values from ad_serdes_out.v as follows.
i_serdes (
.D1 (16'h7FFF),//(data_s0[l_inst]),
.D2 (16'h8000),//(data_s1[l_inst]),
.D3 (16'h7FFF),//(data_s2[l_inst]),
.D4 (16'h8000),//(data_s3[l_inst]),
.D5 (16'h7FFF),//(data_s4[l_inst]),
.D6 (16'h8000),//(data_s5[l_inst]),
.D7 (16'h7FFF),//(data_s6[l_inst]),
.D8 (16'h8000),//(data_s7[l_inst]),
This resulted in a maximum and minimum flat output being received. Perhaps it would be a better idea to input signals more directly going into the serdes?