Hello, Mark, and thank you for your detailed response !
Looks like you're describing exactly the same effect i've seen on my amp.
But wait .. are you going to say that 8657 really use a "EEPROM-style" trimming technology ?
There're some tutorials (MT-037 for example) from ADI saying there're five basic technologies used to match errors in either wafer or post-wafer process:
1. A DigiTrim technology implying no any EEPROMs and complicated logic on board, but using blowing polysilicon fuses, thus programming weighted DAC resistor values.
2. Laser Trim (used "on-wafer")
3. Zener Zap Trim (used "on-wafer" too)
4. Link Trim (also used "on-wafer")
5. EEPROM Trim implying physical existence of EEPROM memory and some custom logic on die
You're talking about a DigiTrim technology (and 8657 datasheet also says that clearly) but you've mentioned also a EEPROM (NVM) mechanism. In the first case this op-amp should not exhibit any sensitivity to power supply events in such a manner, but in the fifth case it really will do. Am I right ?
So what kind of Trim Process all AD8657s are really exposed to ?