HMC794LP3

Hi,

I’m using HMC749LP3 in a PLL design. Considering residual phase noise, it really stands out between other frequency dividers. However, there are some vague points in its datasheet:

1. First table (Electrical Specification) mentions -153dBc/Hz typical SSB phase noise at 10 kHz offset but as it is shown in “Residual Phase Noise” graph; it is better than -160dBc/Hz in that offset for all division ratios. Why these two are different?
2. Note [1] in page 2 of datasheet, states that setting Bias0 pin to 5V will lead to better phase noise floor, however all graphs (including residual phase noise) are in “Bias0=0V” mode.

What is the residual phase noise in “Bias0=5V” mode?

1. Temperature variation graphs are in “CTRL=0” mode in which the output power is minimum.

Dose HMC794LP3 Temperature variation depend on “CRTL” voltage?

Thank you