LLC_DLL_PHASE makes sure the pixel data has enough setup and hold time from the clock to meet the FPGA input.
I would not trust pixel clock 100%. As the format change there may strange transitions, enough to possibly violate some timing constraint in the FPGA. Once stable it should be trusted for the video path.
Looking again at the pictures above, you may have a color space issue.
Also check the pixel clock and pixel data with a scope to may sure you are getting clean waveforms, not a lot of ringing. Might try lower drive strength is you have ringing.
Also when you have a red screen, make sure the green and blue MSB bits are low all the time.