Hello
Per your description, you should be fine as far as the IO_UPDATE/CSB goes. Just make sure the IO_UPDATE pulse width is wider than the SYNC_CLK period because the SYNC_CLK will run slower than 100MHz initially due to the default state of the RF divider value being 8, right?.
IMPORTANT: If the SCLKs rising edges are slow, coupled with excessive edge jitter or reflections at the midpoint of the signal, it's possible this could be seen by the SPI interface inadvertently as multiple SCLKs and get the SPI out of sequence, thus intermittent programming. I think you'll be OK so just making you aware.