I’m in a bring up process of a new board with the AD9361, I’m seeing the following behaviors after sending the script on the bottom.
What’s work well is:
- SPI interface
- clk_out signal
- Data_clk signal
- BBPLL lock, Done when 0x05E[7]==1
What’s Does not work is:
- No data coming out from the AD936, even when I enable loop mode 0x3F5[0]<=1 , while data is being sent in the Tx direction.
- ENSM stuck in state 4.
- Wait for Charge Pump calibration never complete (Done stays low 0x244[7]==0 or 0x284[7]==0 ).
The only difference from the AD9361 evaluation bord is that the VDD_GPO is connected to 1.3V instead of 3.3V.
I have no idea how to proceeds, any have?
BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz
SPIWrite 3DF,01
ReadPartNumber
SPIWrite 295,14 // Power up XO path (Default)
SPIWrite 2A6,0E // Enable Master Bias
SPIWrite 2A8,0E // Set Bandgap Trim
REFCLK_Scale 40.000000,1,2 // Sets local variables in script engine, user can ignore
SPIWrite 292,08 // Set DCXO Coarse Tune[5:0]
SPIWrite 293,80 // Set DCXO Fine Tune [12:5]
SPIWrite 294,00 // Set DCXO Fine Tune [4:0]
SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 009,07 // Enable Clocks
WAIT 20 // waits 20 ms
//************************************************************
// Set BBPLL Frequency: 983.040000
//************************************************************
SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1
SPIWrite 046,03 // Set BBPLL Loop Filter Charge Pump current
SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1
SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1
SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2
SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy
SPIWrite 043,29 // BBPLL Freq Word (Fractional[7:0])
SPIWrite 042,5C // BBPLL Freq Word (Fractional[15:8])
SPIWrite 041,12 // BBPLL Freq Word (Fractional[23:16])
SPIWrite 044,18 // BBPLL Freq Word (Integer[7:0])
SPIWrite 03F,05 // Start BBPLL Calibration
SPIWrite 03F,01 // Clear BBPLL start calibration bit
SPIWrite 04C,86 // Increase BBPLL KV and phase margin
SPIWrite 04D,01 // Increase BBPLL KV and phase margin
SPIWrite 04D,05 // Increase BBPLL KV and phase margin
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1)
SPIRead 05E // Check BBPLL locked status (0x05E[7]==1 is locked)
SPIWrite 002,DC // Setup Tx Digital Filters/ Channels
SPIWrite 003,DC // Setup Rx Digital Filters/ Channels
SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
SPIWrite 00A,15 // Set BBPLL post divide rate
//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
SPIWrite 010,C8 // PPORT Config 1
SPIWrite 011,00 // PPORT Config 2
SPIWrite 012,02 // PPORT Config 3
SPIWrite 006,0F // PPORT Rx Delay (adjusts Tco Dataclk->Data)
SPIWrite 007,00 // PPORT TX Delay (adjusts setup/hold FBCLK->Data)
//************************************************************
// Setup AuxDAC
//************************************************************
SPIWrite 018,00 // AuxDAC1 Word[9:2]
SPIWrite 019,00 // AuxDAC2 Word[9:2]
SPIWrite 01A,00 // AuxDAC1 Config and Word[1:0]
SPIWrite 01B,00 // AuxDAC2 Config and Word[1:0]
SPIWrite 023,FF // AuxDAC Manaul/Auto Control
SPIWrite 026,00 // AuxDAC Manual Select Bit/GPO Manual Select
SPIWrite 030,00 // AuxDAC1 Rx Delay
SPIWrite 031,00 // AuxDAC1 Tx Delay
SPIWrite 032,00 // AuxDAC2 Rx Delay
SPIWrite 033,00 // AuxDAC2 Tx Delay
//************************************************************
// Setup AuxADC
//************************************************************
SPIWrite 00B,00 // Temp Sensor Setup (Offset)
SPIWrite 00C,00 // Temp Sensor Setup (Temp Window)
SPIWrite 00D,03 // Temp Sensor Setup (Periodic Measure)
SPIWrite 00F,04 // Temp Sensor Setup (Decimation)
SPIWrite 01C,10 // AuxADC Setup (Clock Div)
SPIWrite 01D,01 // AuxADC Setup (Decimation/Enable)
//************************************************************
// Setup Control Outs
//************************************************************
SPIWrite 035,00 // Ctrl Out index
SPIWrite 036,FF // Ctrl Out [7:0] output enable
//************************************************************
// Setup GPO
//************************************************************
SPIWrite 03A,27 // Set number of REFCLK cycles for 1us delay timer
SPIWrite 020,00 // GPO Auto Enable Setup in RX and TX
SPIWrite 027,03 // GPO Manual and GPO auto value in ALERT
SPIWrite 028,00 // GPO_0 RX Delay
SPIWrite 029,00 // GPO_1 RX Delay
SPIWrite 02A,00 // GPO_2 RX Delay
SPIWrite 02B,00 // GPO_3 RX Delay
SPIWrite 02C,00 // GPO_0 TX Delay
SPIWrite 02D,00 // GPO_1 TX Delay
SPIWrite 02E,00 // GPO_2 TX Delay
SPIWrite 02F,00 // GPO_3 TX Delay
SPIWrite 261,00 // Set Rx LO Power mode
SPIWrite 2A1,00 // Set Tx LO Power mode
SPIWrite 248,0B // Enable Rx VCO LDO
SPIWrite 288,0B // Enable Tx VCO LDO
SPIWrite 246,02 // Set VCO Power down TCF bits
SPIWrite 286,02 // Set VCO Power down TCF bits
SPIWrite 249,8E // Set VCO cal length
SPIWrite 289,8E // Set VCO cal length
SPIWrite 23B,80 // Enable Rx VCO cal
SPIWrite 27B,80 // Enable Tx VCO cal
SPIWrite 243,0D // Set Rx prescaler bias
SPIWrite 283,0D // Set Tx prescaler bias
SPIWrite 23D,00 // Clear Half VCO cal clock setting
SPIWrite 27D,00 // Clear Half VCO cal clock setting
SPIWrite 015,04 // Set Dual Synth mode bit
SPIWrite 014,05 // Set Force ALERT State bit
SPIWrite 013,01 // Set ENSM FDD mode
WAIT 1 // waits 1 ms
SPIWrite 23D,04 // Start RX CP cal
WAIT_CALDONE RXCP,100 // Wait for CP cal to complete, Max RXCP Cal time: 460.800 (us)(Done when 0x244[7]==1)
SPIWrite 27D,04 // Start TX CP cal
WAIT_CALDONE TXCP,100 // Wait for CP cal to complete, Max TXCP Cal time: 460.800 (us)(Done when 0x284[7]==1)