All the clocks (including DAC, transceiver reference clocks) are generated by AD9523 - using the 125M crystal.
I am not sure of any other way to synchronize this without board modifications.
Charly can give you alternatives and/or more information.
As for driving the DAC with your waveform -- there is no HDL changes planned. The HDL allows you to talk to DAC through the DAC-DMA -- but it is useless for what you are trying to do - it is actually a system limitation. Of course you can do a lot of things in HDL to overcome this limitation - such as using internal buffering, interpolation etc. What you need to do is - bridge the bandwidth that the system can provide and the bandwidth the DAC requires (32Gbps == 1GHz x 32bits). You can change the DDR-FIFO role (currently supports the ADC), you can use the internal memory (has to be a cyclic FIFO -- # of samples limitation) or add interpolation (you will have to generate the samples in parallel). You can also switch to no-OS and get rid of a lot of Linux overhead - perhaps even make the PS7 DDR for ADC, and PL DDR for DAC.
Alternatively, you can slow down the system (reduce the sampling rate) -- (we don't support this in Linux either -- you could try no-OS - might be simple) -- so that the system can handle the bandwidth.