Hi Jim_Jim,
There will be some changes on the datasheet. Below is the recommended /SYNC timing diagram for the AD7763.
The AD7763 goes to /SYNC when the MCLK falling edge senses the /SYNC pin low. This resets the digital filter sequencer to 0. The /SYNC pin must be take low for a minimum of 4 MCLK cycles. When the MCLK falling edges sense the /SYNC has returned to logic high, the AD7763 begins to gather samples simultaneously. Please also take note that /SYNC rising and falling edge stay clear of the MCLK falling edge (as it is sampled on this edge).
Regards,
Jonathan