There are many ways to set the PLL, depending on whether you are writing your own code or using the device drivers and system services furnished with VisualDSP. This code is not device driver code, so how is the function Set_PLL() coded? The only Set_PLL() function I am aware of takes 4 arguments and is used to synchronize the two cores of the BF561. For the BF533, I am assuming this function passes the MSEL (core clock multiplier) and the SSEL (SCLK divisor). If that is the case, then the function must ensure two things:
1> That the SIC_IWR register allows only the PLL interrupt to break the idle command, otherwise all interrupts are enabled by default and any latched interrupt will break the PLL programming sequence.
2> That the proper PLL programming sequence is followed after the write to the PLL_CTL register, namely:
SIC_IWR = 1; // enable only PLL wakeup
*pPLL_CTL = value_with_passed_MSEL;
temp = cli();
idle();
sti(temp);
*pPLL_DIV = value_with_passed_SSEL;
ssync();
If your code sequence respects these requirements and is setting the CCLK and SCLK to valid frequencies, PLL programming should work just fine on the BF533.
-Joe