Hello Daniel,
Sorry this question got lost and did not get answered.
You are correct about the typical frequencies. For 48kHZ fs it is 8x and for 96 kHZ it is 4x etc.
The left and right data is fed on different pins.
The timing diagrams are not detailed for this mode. It does mention that the external filter data is clocked on the rising edge of the BCLK. Since the BCLK falling edge is aligned with the LRCLK rising then I would say that the data is delayed by one half BCLK cycle.
Thanks,
Dave T