Hi Ricky-san,
Based on the given data, the customer is using AD5668-3 (Power-On Reset to Midscale Code). The /CLR pin is falling-edge sensitive. Bringing the /CLR line low clears the contents of the input register and the DAC registers to the data contained in the user-configurable /CLR register and sets the analog outputs accordingly. The clear code values are user-programmable by setting two bits, Bit DB1 and Bit DB0, in the /CLR control register. The default settings clears the outputs to 0V.
Regards,
Mark