Hi Doug,
Thanks for quick response.
We are capturing ADC samples inside FPGA. Just to give you a brief idea about our board:
1. It has 5 ADC chips, AD9253.
2. We are interfacing all the ADC chips in FPGA.
3. SPI programming happens via NIOS processor in control FPGA.
4. This is for 16x20 Large MIMO system.
As requested by you:
1. I am attaching the samples captured in FPGA.
2. File "ADC_Chip_1_Ch_1_ON_Ch_234_PWDN.jpg"--> Ch-1 is only enabled but other channles are PWDN. Still you can see some activity on Ch-3 & 4. It is more on Ch-3.
3. File "ADC_Chip_5_All_Ch_17-to-20_PWDN.jpg"--> This entire ADC chip-5 is power down but still you can see activity on one channel (Ch-17 in the image).
Thanks & Regards
Avnish