is zed output data timing to ad9364 right

The figure shows the output timing when use zedboard transfer data to fmcomms4.The sdk software use the file no-OS/ad9361/sw at master · analogdevicesinc/no-OS · GitHub  but AD9361_InitParam default_init_param is edited to:

0,  //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable

0,  //two_t_two_r_timing_enable *** adi,2t2r-timing-enable

I want to know whether the output timing is right or not. I think the valid signal(dac_valid_i0/i1/s) and data bus(dac_data_i0/q0/i1/q1[15..0]) should be hold 2 clock,but not 4 clock.Please confirm them for me.Thanks.