Hi,
Did r.daemon answer your question? The configuration register we are talking about is a 14-bit register, CFG[13:0], used to configure the ADC for the channel to be converted, the reference selection, and other
components. More details can be found in the Configuration Register, CFG section and Table 9 has the register bit details. As stated in the datasheet, "The register can be written to during conversio,n during acquisition, or spanning acquisition/conversion and is updated at the end of conversion, tCONV (maximum). There is always a one deep delay when writing the CFG register. Note that, at power-up, the CFG register is undefined and two dummy conversions are required to update the register."
Hope this helps.
Regards,
Karen