Hi all,
I have a ADV7611 system working with the Avnet IMAGEON FMC card and a Xilinx FPGA. Things work great at resolutions below 1080p - get video from a PC with a conventional ATI video card over its DVI connector, send it to the ADV7611 through a DVI-to-HDMI cable, through FPGA, out from ADV7511 to DVI, and ultimately to a 1080p-capable monitor. 7611 registers are configured using the "script" that has been made available on the Wiki. This works for stuff like 720p, XGA, WXGA, etc. Input resolution to ADV7611 is controlled by PC's video resolution setting (control panel) in Windows, and HPD is controlled by the FPGA - held high after ADV7611 is configured on boot.
Everything falls apart when the PC is set to output 1920x1080p. For some reason the ADV7611 reports video as interlaced - the appropriate bit in register 0x05 is set... Vertical line count is 540 which sorta makes sense for 1080i I guess, but that's not what I'm outputting from the PC... The resulting settings would normally be passed to the ADV7511 to configure its output, but I'm not sure how to proceed here. Can the vertical line count, front/back porch and sync pulse settings, corresponding to 1080i, be assigned to the ADV7511? Why does the 7611 even see this as interlaced in the first place?!
I tried to modify my ADV7611 driver to support interlaced, and now look at the appropriate registers for when interlaced is defined. This fails to create the valid 4:2:2 video from 7611 to 7511 that works perfectly at lower resolutions. Does anyone know what's going on? Why did interlaced come up at all - has anyone run into this before?
Thanks!