Hi,
You are correct, the LVDS signals need to be terminated into a resistive load, common value is 100ohms. Many applications need to ac couple the signal into this termination to avoid common mode mismatch. This is discussed on page 23 of the data sheet.
The diagrams on page 21 are for the analog input, where the series resistors and shunt capacitor help suppress the transients from the core ADC switching between sample and hold modes.
Regards,
David