Currently i'm using zc702 + fmcomms3 and Vivado 2014.2, ISE 14.7
I met an error following the instruction of Building on Vivado [Analog Devices Wiki]
the error message is :
ERROR: [BD 5-216] VLNV <xilinx.com:ip:processing_system7:5.3> is not supported for this version of the tools.The latest version is:5.4
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
while executing
"create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7"
invoked from within
"set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 sys_ps7]"
(file "../../../projects/common/zc702/zc702_system_bd.tcl" line 27)
while executing
"source $ad_hdl_dir/projects/common/zc702/zc702_system_bd.tcl"
(file "system_bd.tcl" line 2)
while executing
"source system_bd.tcl"
(procedure "adi_project_create" line 94)
invoked from within
"adi_project_create fmcomms2_zc702"
(file "./system_project.tcl" line 7)
I built the project file which is in \hdl\project\fmcomms2\zc702\system_project.tcl after building every .tcl files in library.
the message above shown up again even after clean \hdl folder and re-building libraries.
I"V SEARCHED FOR SOLUTION https://ez.analog.com/thread/42721
and followed rejeesh's guide.
"add ip" - "ZYNQ7 Processing System" (its' vlnv is xilinx.com:ip:processing_system7:5.4) ,
the Tcl Consol shows :
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 processing_system7_0
create_bd_cell: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 623.703 ; gain = 15.113
endgroup
and ZYNQ Processing System is added to Diagram 
what should i do more to process it completely? (and see a SDK_Export folder which should be created in ../fmcomms2_board.sdk/SDK ?)