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Re: ADV7181D 12 bit RGB 4:4:4 DDR mode

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Please reference http://www.quantumdata.com/pdf/882E_HDMI_UG_RevA36.pdf  Appendix D.  gives a quick view of samples and clock rates

 

SD 1x1 525i has one sample per pixel giving 720 samples per active video per line at 13.5MHz

SD 2x1 525i has two samples per pixel giving 1440 samples per active video per line at 27MHz

SD 4x1 525i has four samples per pixel giving 2880 samples per active video per line at 54MHz

 

The pixels output at the samples per active line listed above.  If we were running YCbCr 422 across 16 data lines then LLC would be 13.5/27/54MHz respectively.  If we decided to run TCbCr 422 across only 8 data lines then the pixel rates stay the same but the 'CbCr' has to be interleaved with the 'Y' giving us 27/54/108 LLC and data rate.  The device can not do 108MHz LLC so SD 4x1 525i is not allowed on an 8 bit bus.

 

Now assume we are doing SD 2x1 525i RGB.  The only way to do this is in DDR mode with the data rate coming out at 54 MHz but LLC is 27MHz.  The limitation is the data bus at 54MHz.

 

The bottom line is the device can't do SD 4x1 525i RGB 444, the the tables are still correct.  .


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