Hi rockybooth,
I'd like to add some clarifications on this issue.
The AD7799 operates with an internal master clock only – there is no option to drive the part with an external clock. Therefore, there is no way to completely synchronise several AD7799 devices.
If you use a common SCLK and apply 32 1's synchronously to several AD7799 devices, the devices will be synchronized to a degree i.e. there is still the possibility that conversions are asynchronous by one MCLK cycle (1/64 kHz = 15.625us).
All the SPI lines except the CS can be tied together. You can then take CS of one device low, poll its DRDY pin. When DRDY goes low, you know that all parts have converted once you allow an additional 15.625 us.
Regards,
Johnny