Hello Eugene,
Regarding how to stream your own data, you could disconnect the DMAC from the AXI_AD9122 fifo inputs and connect your own HDL core there. In this case, you can use the no-os software configured as you would send data from the DMA.
Data format (from axi_9122_core.v) :
dac_data_i0 <= dac_ddata[15: 0];
dac_data_i1 <= dac_ddata[15: 0];
dac_data_q0 <= dac_ddata[31:16];
dac_data_q1 <= dac_ddata[31:16];
dac_data_i2 <= dac_ddata[47:32];
dac_data_i3 <= dac_ddata[47:32];
dac_data_q2 <= dac_ddata[63:48];
dac_data_q3 <= dac_ddata[63:48]
Regarding how to In order to see data from the output of the DAC using chipscope, you can connect an ILA core to the dac_dbg_data and dac_dbg_trigger ports.
The format of the data (from axi_ad9122.v) :
assign dac_dbg_data[ 15: 0] = dac_data_i0_s;
assign dac_dbg_data[ 31: 16] = dac_data_i1_s;
assign dac_dbg_data[ 47: 32] = dac_data_i2_s;
assign dac_dbg_data[ 63: 48] = dac_data_i3_s;
assign dac_dbg_data[ 79: 64] = dac_data_q0_s;
assign dac_dbg_data[ 95: 80] = dac_data_q1_s;
assign dac_dbg_data[111: 96] = dac_data_q2_s;
assign dac_dbg_data[127:112] = dac_data_q3_s;
assign dac_dbg_data[128:128] = dac_frame_i0_s;
assign dac_dbg_data[129:129] = dac_frame_i1_s;
assign dac_dbg_data[130:130] = dac_frame_i2_s;
assign dac_dbg_data[131:131] = dac_frame_i3_s;
assign dac_dbg_data[132:132] = dac_frame_q0_s;
assign dac_dbg_data[133:133] = dac_frame_q1_s;
assign dac_dbg_data[134:134] = dac_frame_q2_s;
assign dac_dbg_data[135:135] = dac_frame_q3_s;
Hope this helps.
Regards,
Adrian